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The present situation concerning integrated circuits suggest that clock frequencies of new processing systems are close to their technically feasible maximum. In contrast, the average size of transistors is still dropping. Therefore the complexity of processing systems and the number of employed transistors is increasing further. The paradigm of increasing the clock frequency to reach higher data throughputs is more and more surrogated by increasing the concurrency of new applications. Modern processing systems apply process pipelines internally to increase the degree of parallelism when executing imperative programs. The components implementing the pipeline steps are fixed within the employed processing system and can not be affected by the application developer.

Custom hardware designs containing pipelines, specifically tailored to the application domain, can potentially reach the maximum of possible concurrency. Developing and debugging hardware designs using hardware description languages is a tedious process, including long compilation periods and requiring multiple different skillsets. High-level synthesis (HLS) development environments allow debugging and evaluation of hardware designs at higher levels of abstraction. Applications written in high-level programming languages such as C++ can be validated with accustomed software development tools. The High-level synthesis process creates hardware designs from these high-level application descriptions.

In this thesis, we employ a design process tailored to High-level Synthesis to create a hybrid software/hardware system. From the algorithm description, we create a intial software implementation. Parts of the application will then be synthesized to hardware components. We use the Xilinx Vivado tools to analyze the generated hardware components and create a pipelined system with a high degree of concurrency. The system will be deployed on a device providing a processing system and a field programmable gate array (FPGA). The software component will be deployed on the processing system. The High-level synthesis produces a bitstream that implements the accelerator components on the FPGA. We use the tool suite to profile the deployed system and optimize the data throughput. The result is a highly pipelined application completely implemented in HLS code.