Bookshelf

Cost models play an important role when making design decisions for efficient soft-ware systems. These models can be embedded in operating systems and execution environments to optimize execution at run time. Adapting such models to new hardware architectures requires them to reflect more and more of the paradigms available to modern parallel computing systems. This thesis provides an overview of parallel cost models and describes that with the advent of non-uniform memory access architectures (NUMA), new models have been developed and the priorly existing ones need to be refined. Therefore, the existing NUMA models are analyzed, and a two-step strategy is proposed that incorporates low-level hardware counters as performance indicators. This thesis further focuses on these low-overhead hardware counters, which are available to all modern CPUs. For four major CPU vendors — ARM, AMD, Intel, and IBM — hardware counter specifics are presented and explained in detail. Four tools are developed, all accumulating and enriching specific counter information, to explore, measure, and visualize these low-overhead performance indicators. EvSel allows for measuring the whole plenitude of available counters. Two configurations of a program can be compared, and regressions from program parameters to performance indicators can be computed. Phasenprüfer attributes indicator measurement records to distinct ramp-up and calculation phases automatically. Memhist reveals the latency cost distribution of memory accesses — a major cost factor of recent programs. For analyzing NUMA systems, Hydralisk artificially strain individual interconnect links while simultaneously measuring their bandwidths. All mentioned tools are showcased and discussed alongside specific experiments in the realm of performance assessment. The tools can be obtained and contributed to in a GitHub repository.